Timing and Area Recovery for Serial I/O Iterface

摘要

Physical design is a step in VLSI design cycle which involves the conversion of register transfer level description into a physical layout. With the increase in complexity of the design, the software implementation of algorithms by the EDA tools is necessary for different stages of IC design. Despite the sophistication of EDA tools, sometimes the performance criteria is not met due to the stringent design rules. So, understanding the particular design and providing the necessary constraints is necessary in order to optimize the design. This paper focuses on timing and area optimization of a design in the physical design flow.