Hybrid Variable Latency Carry Skip Adder

摘要

The hybrid variable latency carry skip adder (HVL-CSKA) is obtained by structural modification of the concatenation and incrementation scheme carry skip adder (CI-CSKA). CI-CSKA uses AND-OR-INVERT (AOI) logic and OR-AND-INVERT (OAI) logic as the skip logic instead of multiplexers as in the conventional carry skip adder. While the AOI and OAI logic helps to improve the speed of the adder along with concatenation and incrementation schemes, the hybrid variable latency structure helps to decrease the power consumption without compromising the speed of the adder. Since full adders form the backbone of a CSKA, the basic structure of full adder (FA) is replaced by a high speed and low power structure for FA for further enhancement in the performance of CSKA. The simulations are carried out by using the software Xilinx ISE 14.7 Design suite and Vivado Design suite 2014.4. The hardware used for implementation is Nexys 4 DDR Artix-7 FPGA board. The structures of the adders are compared based on the parameters such as power dissipation, delay, Power-Delay Product (PDP) and area. HVL-CSKA structure shows a decrease of 22.08 percent and 16.56 percent in delay when compared to conventional CSKA and CI-CSKA respectively. While its power consumption is reduced by 70 percent when compared to other structures of CSKA.