Novel Low-Complex 4×4 and 16×16 Intra-prediction Architecture for Error Concealment for H.264

摘要

There are various advanced video-displaying instruments which are responsible for producing high-resolution video data. Due to damaged disk like DVD or other media player, there is huge probability of distortion occur in reproduced video data. Error concealment technique is at decoder side, which has been developed to recover the damaged or lost region by utilizing temporal/spatial redundant information using intra/inter-mode prediction. This phase of intra-prediction mode decision in H.264/AVC intra-frame coder consumes more time with high computational complexity due to iterative process of prediction. Now, for real-time application the novel VLSI architecture for intra-prediction was developed which reduces redundancy and high number of memory access. This proposed architecture is implemented for all nine modes, and novel architecture is processing for 4 × 4 as well as 16 × 16 block size for intra-prediction modes. The proposed hardware design is implemented in VHDL with target device vitex6 (xc6vlx75t-3ff484). This proposed method provides rearrangement of intra-prediction equations, which reduced computational complexity by reducing gate count, and also minimizes iterative process by 29 clock cycle for one macroblock retrieval. Compared to state of the art, the proposed architecture reduces computational complexity.