Comparative study of interconnect network on chip topology in multicore processors

摘要

A variety of technologies in recent years have been developed in designing on-chip networks with the multicore system. In this endeavor, network interfaces mainly differs in the way a network physically connects to a multicore system along with the data path. Semantic substances for interaction in a multicore system are transmitted as data packets. Thus whenever a communication is made from a network, data packet is first divided into sub-packets and then into non varying-length bits for flow control. To measure required space, energy & latency overheads for the implementation of various interconnection topologies we will be using multi2sim simulator tool that will act as research bed to experiment various trade offs between performance and power, and between performance and area requires analysis for further possible optimizations.