Incorporating FPGA-based acceleration in high performance systems demands efficient generation of complete system architecture with multiple accelerators, memory hierarchies, bus structures and interfaces. In this work we explore a set of heuristics for complete system generation, with the objective of developing automatable methodology for system level architectural exploration and generation. Our experimental analysis on two test cases demonstrates that applying a set of system optimization heuristics incrementally on a baseline system configuration, we can converge to efficient system designs and reach target performance.
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