Effect of N-well for single event upset in 65 nm CMOS triple-well technology in 6T SRAM CELLS

摘要

In this paper, the effect of N-well for single event upset in 65nm CMOS triple well technology SRAM CELLS is studied. The study shows that charge sharing collection increases because of the existing of N-well in triple-well technology. While it restrains the single event upset and reduces the soft error rate (SER) compared with the SRAM whose NMOS are dual-well technology devices. The result of this work can provide a way to protect integration circuits from single event effect (SEE) and soft errors.