The Design and Implementation of DDR PHY Static Low-Power Optimization Strategies

摘要

The static power of DDR PHY has increasingly become the limit of the low-power application of system-on-a-chip (SoC). An optimization of static power based on "behavior" and "state" of DDR PHY static power is proposed, considering the design principle and physical properties. Experimental results show that the proposed optimization strategy can achieve the highest 59.12percent reduction in work mode and only 0.723uW power consumption in sleep mode.