Flip-flop design has emerged as an important issue for low power designs. In this paper, we have tackled this problem and proposed a new technique, conditional discharge technique, to reduce the redundant switching activity of the internal nodes in flip-flops. Moreover, Double-edge triggering concept is utilized to further reduce the power consumption in the clock distribution network The outcome of this work is two new flip-flops: explicit pulsed Conditional Discharge Flip-Flop (ep-CDFF) and implicit pulsed Conditional Discharge Flip-Flop (ip-CDFF). With a data switching activity of 37.5%, these new flip-flops can achieve 15% energy savings.
展开▼
