首页> 外文会议>ASME International Mechanical Engineering Congress and Exposition >EFFECT OF GUARD RING DESIGN AND PROPERTIES OF INTER-LAYER DIELECTRIC FILM ON CHIP RELIABILITY
【24h】

EFFECT OF GUARD RING DESIGN AND PROPERTIES OF INTER-LAYER DIELECTRIC FILM ON CHIP RELIABILITY

机译:层间介电膜的防护环设计与性能对芯片可靠性的影响

获取原文

摘要

One of the common reliability problems in semiconductor industry is delamination of dielectric films used in the integrated circuit manufacturing process. Although these films have demonstrated good reliability performance in wafer form, once placed in different packages and undergo stress testing (e.g. pressure cooker test) they tend to crack and delaminate and lead to eventual reliability failure of the chip. The die guard ring can impact propagation of cracks that are initiated at the edge of the die into the active circuitry of the die. We designed several guard ring structures and performed finite element analysis to compare the potential of crack propagation for different guard ring designs. It is found that some features of the design do not affect stress intensity factor K_I (potential of crack propagation). For long crack (3.75 um), structure A may reduce K_I. But, structure B will increase K_I. From fracture mechanics point of view, structure A may stop crack propagation toward die center. However, with structure B, the crack may still penetrate into the die. For short crack (1.25 um), effect of guard ring structure design is negligible. We have made experimental wafers using our wafer manufacturing processes to create structure A and B around the dice. Some wafers were made with film AA as interlayer dielectric and some with film BB as interlayer dielectric. SEM inspections validate our FEM models that structure A captures more cracks at the edge of the die and prevents its propagation into the die while structure B is less effective. We have shown that even with incorporation of structure B guard ring, film BB looses adhesion to other layers and delaminates upon exposure to humidity in pressure cooker test while film AA never delaminates.
机译:半导体行业中的一个共同可靠性问题是在集成电路制造过程中使用的介电膜的分层。虽然这些薄膜在晶片形式中表现出良好的可靠性性能,但是一旦放置在不同的包装中并经过压力测试(例如,压力炊具测试),它们倾向于裂开和分层并导致芯片的最终可靠性失效。管芯防护圈可以冲击在模具边缘发起的裂缝的传播,进入模具的有源电路。我们设计了多个保护环结构,并进行了有限元分析,以比较不同防护环设计的裂纹传播的潜力。发现设计的一些特征不会影响压力强度因子K_i(裂缝传播的电位)。对于长裂纹(3.75℃),结构A可以减少K_I。但是,结构B将增加K_I。从断裂力学的角度来看,结构A可能会阻止裂缝向模具中心传播。然而,利用结构B,裂缝仍然可以渗透到模具中。对于短裂缝(1.25 um),保护环结构设计的影响可忽略不计。我们已经使用晶圆制造工艺进行了实验晶片,以在骰子周围创建结构A和B.将一些晶片用薄膜AA制成,作为层间电介质,一些用薄膜BB作为层间电介质。 SEM检查验证了我们的有限元模型,使得结构A在模具的边缘处捕获更大的裂缝,并防止其在结构B不太有效时传播到模具中。我们已经表明,即使采用结构B保护环,薄膜BB也会在暴露于压力锅测试中暴露于湿度时对其他层和分层的粘附性,而薄膜AA从未分分层。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号