integrated circuit layout; system-on-chip; low-power electronics; reference circuits; compensation; modulators; current mirrors; MOSFET; bandgap reference; chopped modulator; MOSFET mismatch; SOC application; chip layout; current-mirror mismatch; chopper modulator; opamp offset; CMOS process; system-on-chip; 1 to 1.5 V; -20 to 60 C; 4 muA; 0.3 mm; 0.4 mm; 0.12 mm; 0.25 micron;
机译:低温带隙参考电路,具有紧凑模型参数提取MOSFET和BJT的HPGE探测器
机译:在40 nm工艺下基于不同阈值MOSFET的低于1 V带隙基准
机译:使用亚阈值MOSFET的带隙基准电压的高阶曲率补偿技术
机译:具有斩波调制器的高精度带隙基准,可补偿MOSFET的失配
机译:斩波器缓冲的相互补偿的迁移率和阈值CMOS电压基准
机译:通过应变工程在具有大晶格失配的核/壳纳米线中实现可广泛调谐的GaAs带隙
机译:具有电阻变化的带隙参考补偿