VLSI implementation of a self-checking self-exercising memorysystem

摘要

A VLSI implementation of a design concept for a self-checkingself-exercising (SCSE) memory system described by D. Rennels and S. Chau(see Proc. 16th Int. Symp. on Fault-Tolerant Computing p.358-63 (1986))is presented. The design, which provides a way of detecting faults andcorrecting errors in RAMs within milliseconds while concurrentlyperforming normal execution of programs, is reviewed. The approach is toadd two parity bits to each row in the storage arrays of the RAM chipsand to provide hardware scrubbing interleaved with normal programcycles. The RAM and MIBB (memory interface building block) chip designs,and some of the augmentations and changes required from the originalconceptual design, are examined. The approach has been determined to befeasible, and the three-year design process has also demonstrated thelarge distance between a conceptual design and its realization. Errorsand deficiencies were found in the original design and corrected, andnew useful functions were identified and added