A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT

摘要

As the technology node is evolving, standard cell (SDC) design scaling is obstructed by design constraints such as limited routing resources, lateral P-N separation, and performance requirements. Complimentary-FET (CFET) technology, which stacks the P-FET on N-FET or vice versa, is able to release the restriction of P-N connection for SDC layout scaling. However, (both in-cell and block-level) routable CFET SDC design, while maintaining the scaling advantages, is a non-trivial problem because of the extremely limited routability (including pin-accessibility) comes from the intrinsic stacked FET structure. In this paper, we propose an SMT (Satisfiability Modulo theories)-based framework to automate CFET SDC synthesis through the simultaneous place-and-route optimization methodology with a novel Dynamic Complimentary Pin Allocation scheme. Moreover, our framework generates optimized CFET SDC layouts in terms of routability through our novel pin access and routing resource related objectives/constraints, while the scaling advantage of CFET structure is maintained compared to conventional FET structure. We demonstrate that CFET cell structure provides 10.1/22.2% on average reduced cell width and metal length compared to conventional FET structure. Moreover, we validate that our routability-driven features successfully improve routability in practical circuit designs through block-level analysis. Compared to the previous work, our routability-driven framework improves 4.2% utilization and reduces 83% routing errors on average in block-level designs.