Modelling Error Pulses in a CMOS Triple Majority Gate while Exposed to an Ionizing Particle

摘要

Modelling results for noise pulses forming by logical elements are presented when collecting charge from the single particle tracks with wide range of the linear energy transfer of 10–90 MeV∙cm²/mg. This performs using 3D CAD physical models of CMOS transistors designed on 65 nm bulk technology with shallow trench isolation of transistor groups. The main positive thing that happens when collecting the charge at the linear energy transfer more 40 MeV∙cm²/mg from the track in the group of NMOS transistors belonging to element OR and in the group of PMOS transistors belonging to element AND is holding these transistors in the mode when all transistors are collecting charges. This forms a delay of noise pulses on the outputs of elements and decreases its duration.