Improved Parallel-IDMA Architecture with Low-Complexity Elementary Signal Estimators

摘要

This paper presents a low-complexity parallel multiuser detector architecture for interleave division multiple access systems. To facilitate efficient hardware implementation, the formulae associated with the elementary signal estimator (ESE) are reorganized. Grounded on the reorganization, the proposed ESE circumvents redundant computations, and takes advantage of carry-save additions. The resulting datapath is further simplified by approximations that do not deteriorate the error rate noticeably. Prior to integrating with such ESEs, the state-of-the-art parallel architecture for the user-specific processing block (UPB) is also simplified by rescheduling the memory-access pattern. As a result, a prototype 2-parallel 16-user detector that incorporates the proposed ESEs and UPBs in a 65-nm CMOS occupies 23% less silicon area, dissipates 21% less power, and takes 50% less latency than the state-of-the-art serial detector.