10.8 A 4-Element 500MHz-Modulated-BW 40mW 6b 1GS/s Analog-Time-to-Digital-Converter-Enabled Spatial Signal Processor in 65nm CMOS

摘要

Next-generation phased-array systems with large modulated bandwidths (BW) and high energy efficiency will enable Gb/s wireless communications. The spatial signal processing at this large scale using state-of-the-art phase-shifter (PS)-based arrays causes unsolved challenges in dense interference-limited networks with large modulated BWs. In addition, the need for frequency-independent array gain demands low-complexity and energy/area-efficient true-time-delay(TTD)-based spatial signal processing. Recent works have demonstrated beam-nulling [1], [2] and beamforming [2]–[4] for PS and TTD systems. In [1], a baseband(BB)-to-RF impedance translation is used for beam nulling with a swept single tone only. In [2], an autonomous spatial filter without external controls is implemented for large modulated BW. However, its PS-based method introduces frequency-dependent filtering for applications at lower RF carrier frequencies (large fractional BWs). To avoid beam-squint in beamforming, the digital TTD-based beamformer is implemented in [3] with 100MHz BW; however, the required 16 ADCs (1/element) increases the overall RX power consumption. In [4], a 100MHz analog BB beamforming architecture implementing TTD in the clock path is shown. However, the switched-capacitor implementation is insufficient to support large modulated BWs with high energy efficiency for next-generation communication links.