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94 power-recycle and near-zero driving-dead-zone N-type low-dropout regulator with 20mV undershoot at short-period load transient of flash memory in smart phone

机译:在智能手机中闪存的短期负载瞬态期间,具有94m%的功率循环和接近零的驱动死区N型低压降稳压器,具有20mV的下冲

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In power-management integrated circuits (PMIC) for smart phones, cascaded buck and low-dropout (LDO) regulators with N-type power MOSFETs are commonly utilized for high conversion efficiency, power quality and high-density integration as shown in Fig. 27.8.1 [1]. Long paths on printed-circuit board (PCB) from the PMIC to the following applications result in obvious parasitic effects of large LPCB and RPCB, and multilayer ceramic capacitors (MLCC) placed near the application side are necessary. Complex and unpredictable PCB networks induce unexpected poles and zeros in the LDO loop so that an LDO with wide bandwidth (BW) and fast transient response is difficult to design. Furthermore, flash memory, such as universal flash storage (UFS) and embedded-multimedia cards (eMMC), has short-period heavy-to-light-to-heavy (H-L-H) load transients which makes LDO design more challenging. In the waveform shown in Fig. 27.8.1, the gate voltage of the power MOSFET (VGATE) is pulled toward 0V when overshoot of VOUT is caused by a heavy-to-light load transient. Once the light-to-heavy load transient occurs at moment t0 with VOUT overshoot, VOUT then suffers from large undershoot because the N-type power MOSFET has a driving dead zone. The driving dead zone is defined as the region of gate voltage VGATE lower than the VOUT level and the power MOSFET delivers no current. The power MOSFET and compensation capacitance forms a heavy capacitance load so that transient performance is degraded. In prior art, the amplifier (amp) and buffer stage consume large quiescent current (IQ) for easier stability compensation and higher slew rate (SR). In addition, dummy load current (Idummyload) at VOUT or a complex clamping function at VGATE are utilized for the short-period H-L-H load transient of flash memory. However, the efficiency and circuit complexity are sacrificed as a result.
机译:在智能手机的电源管理集成电路(PMIC)中,通常使用具有N型功率MOSFET的级联降压和低压降(LDO)稳压器来实现高转换效率,电能质量和高密度集成,如图27.8所示。 .1 [1]。从PMIC到以下应用的印刷电路板(PCB)上的长距离路径会导致大型L PCB 和R PCB 以及多层陶瓷电容器(MLCC)的明显寄生效应)放在靠近应用程序一侧的位置是必要的。复杂且不可预测的PCB网络会在LDO环路中引起意外的零点和零点,因此难以设计具有宽带宽(BW)和快速瞬态响应的LDO。此外,诸如通用闪存(UFS)和嵌入式多媒体卡(eMMC)之类的闪存具有短暂的重载到轻载到重载(H-L-H)负载瞬态,这使得LDO设计更具挑战性。在图27.8.1所示的波形中,当V OUT 的过冲引起重功率时,功率MOSFET(V GATE )的栅极电压被拉至0V。到轻负载的瞬态。一旦在t 0 时刻出现轻到重负载瞬变且V OUT 过冲,则V OUT 会遭受较大的下冲,因为N型功率MOSFET具有驱动死区。驱动死区定义为栅极电压V GATE 低于V OUT 电平的区域,并且功率MOSFET不提供电流。功率MOSFET和补偿电容会形成沉重的电容负载,因此瞬态性能会下降。在现有技术中,放大器(amp)和缓冲级消耗大的静态电流(I Q ),以实现更容易的稳定性补偿和更高的压摆率(SR)。此外,短周期HLH使用V OUT 处的虚拟负载电流(I dummyload )或V GATE 处的复数钳位函数闪存的瞬态加载。但是,结果是牺牲了效率和电路复杂性。

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