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Design of CMOS imaging system based on FPGA

机译:基于FPGA的CMOS成像系统设计

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In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.
机译:为了满足滚动快门模式下高动态范围CMOS相机的工程应用需求,基于CMOS成像传感器NSC1105设计了完整的成像系统。本文将CMOS + ADC + FPGA + Camera Link确定为处理架构,并介绍了硬件系统的设计和实现。对于由CMOS时序驱动模块,图像采集模块和传输控制模块组成的摄像头软件系统,本文采用Verilog语言进行设计,并基于Xilinx FPGA驱动其正常工作。 ISE 14.6仿真器ISim用于信号仿真。成像实验结果表明,该系统具有1280 * 1024像素分辨率,帧频为25 fps,动态范围超过120dB。系统的成像质量满足指标要求。

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