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Atomically thin graphene plane electrode for 3D RRAM

机译:用于3D RRAM的原子薄石墨烯平面电极

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3Å thick graphene edge was employed in the bit-cost scalable vertical RRAM structure to drastically reduce the total stack height to a single atomic layer. Two-layer 3D-stacked HfO RRAM with graphene planar electrode (G-RRAM) is demonstrated in a 3D cross-point architecture with the edge of the graphene plane electrode serving as the bottom electrode of the RRAM. Exceptional memory window (>80×), low reset current (~20 μA), and suitable set/reset voltages (2 to 4 V) were achieved. Large memory window and low SET compliance ensures low reset current and low power consumption. Resistance components were separately measured to verify the role of graphene/oxide interface and the graphene sheet resistance. This work is a significant step toward extreme vertical scaling of 3D vertical stacked memory structures.
机译:在位成本可扩展的垂直RRAM结构中采用了3Å厚的石墨烯边缘,以将总堆叠高度大大降低至单个原子层。在3D交叉点架构中演示了具有石墨烯平面电极(G-RRAM)的两层3D堆叠HfO RRAM,其中石墨烯平面电极的边缘用作RRAM的底部电极。实现了出色的存储窗口(> 80x),低复位电流(〜20μA)和合适的设置/复位电压(2至4 V)。大存储器窗口和低SET合规性确保了低复位电流和低功耗。分别测量电阻组件,以验证石墨烯/氧化物界面和石墨烯薄层电阻的作用。这项工作是朝3D垂直堆叠内存结构的极端垂直缩放迈出的重要一步。

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