A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies

摘要

A new scheme called in the following “Diffusion and Gate Replacement” (D&GR) MIPS integration is demonstrated. The CMOS flow allows to control the gate height asymmetry between NMOS and PMOS by driving the work function shifter directly into the high-k. Since the threshold voltage (Vth) shifter sources are removed, it is compatible with other processes requiring high-thermal budget such as memory technologies (DRAM periphery).