A 10-b 40-MS/s Pipeline ADC with a Novel Low-Variation On-Resistance CMOS Input Sampling Switch

摘要

A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13μm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing with 2.5-bit/stage and an improved amplifier sharing scheme, very competitive power consumption and small die area can be achieved. A test chip was fabricated for confirmation, a peak signal-to-noise-plus-distortion ratio (SNDR) of 56.76 dB with 40MS/s at 19.3 MHz input signal and a power dissipation of 23.2 mW was achieved.