In recent years, the clock frequency, the number of cores, and the power dissipation of application processors (APs) for portable electronics have dramatically increased. As a result, peak processor currents have reached several amperes with slew rates on the order of 1As. These fast large steps incur large output voltage (VOUT) droops, which induce failed paths and cause processor black-outs. Present voltage regulators (VRs) combat these challenges by using bulky output capacitor (COUT) arrays that could add up to over 100μF. However, this practice is untenable for next-generation APs, which have severely limited PCB area and require fast dynamic voltage scaling. These challenges have led to great demand for ultra-fast VRs. PWM control requires a bandwidth 5 to 10× less than the switching frequency, fSW, which results in a slow response [1]. Hysteretic control has been proposed to achieve faster response [2, 3], however, it still suffers from an inherent delay (tdelay) up to the discharge period, (1-D)T, due to realistic hysteretic window size and inductor current (IL) slew limit. Consider, for example, a fast hysteretic VR achieving 10% voltage droop for an instant load step of 5A. For an inductor (L) chosen to have IL ripple < 200mA, and COUT under a few μF, tdelay cannot exceed a few ns. This requires a fSW from 0.5 to 1GHz, which in turn causes a large switching loss and restricts the feasible power level of the converter. This is against the power demand trend of APs. An interleaved multiphase topology can be the most effective way to improve both the system response and the equivalent IL slew rate by changing the number of phases; however, clock and phase synchronization and current sharing for conventional hysteretic control are challenging.
展开▼
