Manufacturability optimization and design validation studies for FPGA-based, 3D integrated circuits

摘要

Heterogeneous integration of integrated circuits offers an opportunity to create new functionality with tradeoffs between cost, performance, and alternative monolithic integration complexity. We present a study of heterogeneous integration using a large, field programmable gate array (FPGA) research and development vehicle to assess the capabilities of 3D silicon interposer technology. This study includes integration on a silicon interposer of a monolithic high-performance FPGA product with a companion test chip, manufacturing flow optimization for yield and reliability, design optimization, and characterization studies. High yield and reliability metrics were achieved through stress management, robust design, and manufacturing flow optimizations. Characterization results show minimal performance impact due to through silicon via (TSV) to 10Gbps transceivers and potential improvement in performance by integrating metal-insulator-metal (MIM) capacitor on the silicon interposer. Co-design implications for 3D product integration of large, high performance FPGA's with companion die will be discussed.