Digital phase-locked loops based on bang-bang phase detectors are attractive candidates for frequency synthesizers and clock multipliers because of their simplicity and low power consumption. However, being nonlinear systems, they are proved difficult to analyze and prone to the generation of limit cycles. Under the presence of phase noise originating from the controlled oscillator with 1/f2 and 1/f3 spectral shapes, simple expressions of the output jitter as a function of the loop parameters are developed which allow us to avoid limit cycles and to optimize the design to minimize output jitter.
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机译：基于爆炸性相位检测器的数字锁相环由于其简单性和低功耗而成为频率合成器和时钟乘法器的诱人候选。但是，作为非线性系统，事实证明它们很难分析并且容易产生极限环。在存在源自1 / f 2 和1 / f 3 频谱形状的受控振荡器的相位噪声的情况下，输出抖动作为环路函数的简单表达式开发了一些参数，这些参数使我们能够避免极限周期并优化设计以最大程度地减少输出抖动。
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