A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation

摘要

This paper presents a 0.8-mW 0.2-mm^{2 9-level second-order single-loop SC Delta-Sigma modulator (DΣM) ADC in 1.8-V 0.18-mm CMOS technology for low-power high-resolution sensing applications. The DΣM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dBFS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOMS. The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10-μW resistor-less flash quantizer. The obtained 172.6-dB FOMS is competitive within the state-of-art high-resolution (SNDR > 90 dB) and general-purpose (bandwidth > 20 kHz) SC DΣM ADCs.}