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VHDL implementation of high performance RC6 algorithm using ancient Indian vedic mathematics

机译:VHDL使用古代印度吠陀数学实现高性能RC6算法

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RC6 is the successor to RC5. It is one of the most promising algorithms that is both fast and secure. It uses four w-bit registers, integer multiplication, quadratic equation and fixed bit shifting. This paper examines how the Vedic algorithm of Urdhva tiryagbhyam speeds up the computation of this algorithm when compared with conventional algorithms in existence.
机译:RC6是RC5的后继产品。它是最有前途的算法之一,既快速又安全。它使用四个w位寄存器,整数乘法,二次方程式和固定位移位。与现有的常规算法相比,本文研究了Urdhva tiryagbhyam的Vedic算法如何加快该算法的计算速度。

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