3D integration is a technological innovation that promises improved performance at lower dissipated power of integrated circuits by stacking silicon layers connected with special vertical wires called Thru-Silicon-Vias (TSVs) [1]. The increasing delay and high dissipated power of global interconnects in advanced 2D technologies is not alleviated by replacing these long wires (~mm) with shorter TSVs (~ tens of µm). In 3D systems-on-chip (SoCs), the functional (Intellectual Property IP) blocks are distributed across the layers of the stack. The interconnect fabric on which the system''s IP blocks communicate must ensure high performance and flexibility of designs by implementing communication protocols at different abstraction layers. 3D networks-on-chip (NoCs) are among the proposed solutions for scalable high performance and low power communication. 3D NoCs consists in routing nodes attached to the IP blocks that have intra-die and inter-die links.
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机译：3D集成是一项技术创新，通过堆叠与称为Thru-Silicon-Vias（TSV）的特殊垂直线连接的硅层，可以保证在较低的集成电路功耗下提高性能。通过用较短的TSV（〜数十微米）代替这些长导线（〜mm），并不能缓解先进2D技术中全局互连不断增加的延迟和高耗散功率。在3D片上系统（SoC）中，功能（知识产权IP）模块分布在堆栈的各个层中。系统IP块在其上进行通信的互连结构必须通过在不同抽象层上实现通信协议来确保设计的高性能和灵活性。 3D片上网络（NoC）属于可扩展的高性能和低功耗通信的建议解决方案。 3D NoC包含连接到具有裸片内和裸片间链接的IP块的路由节点。
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