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A frequency-scalable 15-bit incremental ADC for low power sensor applications

机译:适用于低功率传感器应用的可频率缩放的15位增量ADC

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A 15-bit low-power incremental ADC is designed for sensor applications. The ADC is designed to be frequency-scalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18/Ltm CMOS and occupies an area of 0.35mm2. Configured to operate at full-rate as a Delta-Sigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83µW from a 1.8-V supply. Operating as an incremental converter, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 88.9dB peak SNDR while operating from 1.67S/S to 1.67kS/s and scaling analog power by up to 500 times.
机译:15位低功耗增量型ADC专为传感器应用而设计。 ADC被设计为可在1.67S / s至1.67kS / s的频率范围内进行1000倍频率扩展。为了降低功耗,使用了具有AB类特性的运算放大器。该设计采用0.18 / Ltm CMOS制成,面积为0.35mm 2 。 ADC配置为以全速率作为Delta-Sigma调制器工作,该ADC达到91.8dB的峰值SNDR,同时从1.8V电源消耗83µW的功率。 ADC作为增量转换器工作,会定期关闭电源以实现频率可扩展性,并在1.67S / S至1.67kS / s的工作时间内保持SNDR峰值为84.7dB至88.9dB,并将模拟功率扩展至500倍。

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