A multiplierless structure for direct digital IF signal synthesis

摘要

A multiplierless structure using an 8th order band pass (BP) sigma delta (EA) modulator for synthesizing the intermediate frequency (IF) signal is presented in this paper. A fractional delay interpolation filter combining cascaded integrator-comb (CIC) and Lagrange filters is used before the EA-modulators to suppress the image caused by the time-interleaving in the IQ-paths. Closed form formulas for estimating the image suppression ratio (ISR) of different order interpolations are given. The results from the numeric analysis match the estimation well. The proposed structure has been implemented in an FPGA. The implementation results in 70dB image suppression for a band width of 1.56MHz at 25MHz center frequency.