Design of a high-speed (255,239) RS decoder using 0.18 /spl mu/m CMOS

摘要

Reed-Solomon (RS) codes have been widely used in a variety of communication systems and data storages to protect digital data against errors occurring in the transmission process. This paper presents a VLSI implementation of a high-speed, 8-error correcting, RS(255,239) decoder in the 0.18 /spl mu/m CMOS technology. The decoder architecture uses the "division-free algorithm", a modified Berlekamp-Massey algorithm, in the key equation solver and a terminated mechanism in the Chien search circuit. The other key in this implementation is the use of highly efficiently simplified Galois field arithmetic operation circuits. The low-complexity, low latency power-sum and inversion circuits boost up the speed and latency of the decoder. The chip occupies a core area of 1.5 mm/sup 2/ and obtains a data processing rate exceeding 1 Gbit/s.