An overview of low-voltage VCO delay cells and a worst-case analysis of supply noise sensitivity

摘要

This paper presents a comparative study of the architecture and timing jitter of the delay-cells of low-voltage CMOS ring-VCOs. Design considerations, such as noise, single-ended versus differential, linearity and symmetry of load, and the output voltage swing of delay cells are examined in detail. The worst-case sensitivity of the delay time of the delay cells and that of the oscillation frequency of corresponding ring-VCO implemented in TSMC 0.18 /spl mu/m CMOS technology are analyzed using Cadence's Spectre with BSIM3v3 device models. Simulation results are presented.