Paradys: A scalable infrastructure for parallel circuit simulation

摘要

We detail the design of a scalable infrastructure, called Paradys, developed for parallel circuit simulation. Early measurements of its scalability (some 0.9x of parallel efficiency) are encouraging signs to measure on larger parallel configurations as well as to envision its application for simulation of deep sub-micron technology. This good scalability is, in great part, achieved thanks to a dynamically managed memory gap, called ShMC++, reducing the number of memory accesses in the given shared memory environment. Actual measurements show an increase, due to ShMC++, of the overall speed-up of Paradys parallel infrastructure going from 14% to 78% depending on the original memory access rate.