A spurious reduction technique for high-speed direct digital synthesizers

摘要

Digital-to-Analog Converters (DACs) are the primary source of spurious in high-speed Direct Digital Synthesizers (DDS), DAC glitches, DC-linearity errors, and digital noise feedthrough can corrupt the DDS output. This paper proposes a balanced-DAC configuration at the DDS output that can dramatically reduce these effects. A pair of single-ended DACs are employed, driven from a set of inverters that generate the out-of-phase drive signals. An on- or off-chip subtractor combines the two out-of-phase DAC outputs, canceling distortion, noise, and glitches. Simulations along with experimental results from an 800 MHz balanced-DAC DDS breadboard are included. Greater than 10 dB reduction in harmonics, aliased-harmonics, and noise floor have been achieved. A monolithic version of this balanced-DAC DDS has been fabricated and is currently in test.