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130 nm CMOS Fully Differential SC Filter for Ultra-Low Voltage ∑-Δ Converter

机译:用于超低压Σ-Δ转换器的130 nm CMOS全差分SC滤波器

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In this paper design and function of the fully differential (FD) switched-capacitor (SC) integrator for ultra-low voltage Sigma-Delta analog to digital converter (∑-Δ ADC) are presented. The proposed integrator was designed for differential input signal and applicable as a main analog block of ultra-low voltage ∑-Δ ADC in standard 130 nm CMOS technology. The main block of proposed integrator is operational transconductance amplifier (OTA) based on two-stage Rail-to-Rail (RtR) FD operational amplifier (OPAMP) working in sub-threshold regime. The characteristic properties of this circuit is non-standard OTA topology, using SC common-mode feedback (CMFB) circuit and using switching T-gates. All of these subcircuits are supplied by only 0.6 V with achieved gain 24.09 dB and cutoff frequency 165.95 kHz.
机译:本文介绍了用于超低压Sigma-Delta模数转换器(∑-Δ ADC)的全差分(FD)开关电容器(SC)积分器的设计和功能。拟议的积分器设计用于差分输入信号,并可用作标准130 nm CMOS技术中的超低压Σ-ΔADC的主要模拟模块。拟议积分器的主要模块是基于亚阈值状态的两级轨至轨(RtR)FD运算放大器(OPAMP)的运算跨导放大器(OTA)。该电路的特性是非标准OTA拓扑,使用SC共模反馈(CMFB)电路并使用开关T型门。所有这些子电路仅由0.6 V供电,增益为24.09 dB,截止频率为165.95 kHz。

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