A Implementation for Built-in Self-Testing of RapidIO by JTAG

摘要

With the development of integrated circuit manufacturing process, the transmission rate of high-speed interface circuit is rapidly increasing. High-speed interface develops from traditional digital circuit to mixed-signal circuit. The testing of mixed-mode high-speed circuits in mass production is difficult, time-consuming and costly. This paper realizes the testability design of built-in self-test(BIST) in a typical high-speed interface circuit--RapidIO through JTAG, and completes the verification of internal loop and external loop tests both on simulation phase and product test phase. Comparing with the traditional method using core program to access RapidIO and testing the product with a bit error ratio tester, the design method in this paper has the advantage of operating simply and implementing easily. It completely saves the time of main PLL's locking and the time of loading program from outside the chip. And the configuration time for RapidIO can be saved by one-thirds. What's more, the reliability of configuration through JTAG on ATE is more guaranteed than running function program. It has reduced test time and test cost effectively in the phase of mass production test.