From Tuning to Learning: Why the FPGA Physical Design Flow Offers a Compelling Case for ML?

摘要

MLCAD is particularly suited for the FPGA Physical design (PD) flow since each device family generation innately provides a rich platform for device/design feature data harvesting: (1) A vast amount of device architecture-specific interconnect/layout fabric data and (2) significant amount of large design suite data from and from broad set of application domains. These bode well for developing robust predictive ML models. Furthermore, the long lifespan of these device families affords a favorable ROI. In this talk, we will highlight some data harvesting and ML solutions we have developed in Xilinx’ Vivado PD flow and share some initial results. These include a strategy recommendation framework for design closure, design classification for computational resource allocation, device characteristics modeling, and routing congestion estimation. Furthermore, we will outline potential MLCAD opportunities in trend identification, algorithm parameter optimization, and reinforcement learning paradigms where we foresee potential collaborations with the academic community.