Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking

摘要

Aggressive scaling of circuits to achieve smaller feature sizes has led to an increased concern about their reliability as small scale circuits age faster. Thus, an increase in the number of computational errors due to defects is expected in the nanoscale dimensions. Concurrent error detection techniques including logic implication-based checking can detect a partial number of these errors at lower area costs. In this paper, we evaluate the performance of this mode of error detection in implemented circuits, specifically FPGA circuits where it is possible for a single fault to affect multiple logic paths. Fault injection experiments show that the probability of error detection achieved for circuits that are implemented in FPGAs is significantly less than that predicted by fault simulations on their corresponding netlists, almost by half. It is thus shown that the efficiency of implication relationships in detecting errors not only varies from one circuit to another but that it also depends largely on the implementation of the circuit under test as supported through analytic analyses and experimental results.