On-Chip Implementation of Analog Linearization Schemes for Giant-Magnetoresistance Sensors

摘要

In this paper, on-chip implementation of two linearization schemes for the giant-magnetoresistance (GMR) sensors has been presented. Conventionally, these linearization schemes are implemented in the discrete levels requiring dual supply rails (positive as well as negative), high power consumption, large component-counts and board space. In the proposed work, on-chip solutions are presented using a single supply voltage. Various design techniques are incorporated to enable a low-voltage, low-power operation and enhance the sensitivity of the sensor. The proposed schemes are designed in a 180-nm CMOS process. Preliminary simulation results in the architectural level show the efficacy of the proposed schemes. Integrated simulation results with the previously measured characteristic data of the GMR sensor show a good agreement with the theory as well as their discrete-counterparts.