FPGA Implementation and Acceleration of Convolutional Neural Networks

摘要

In many areas like pattern recognition, object detection, and image classification, Convolutional Neural Networks(CNN) are becoming prevalent. FPGA implementation of a trained CNN model and accelerating the CNN model by parallelizing the operations within layers is proposed in this paper. The evaluation of the proposed model is done using the MNIST digit dataset and is later observed for other datasets as well. The evaluation is done based on the parameters such as accuracy, resource utilization, and speed up a achieved upon parallelization. It is observed that the accuracy obtained on FPGA is the same as the accuracy obtained on the computer and the model achieved maximum speed up of 2.586 on FPGA after parallelization.