FEC BCH: Study and Implementation on VHDL

摘要

Channel encoding and Forward Error Correction is a crucial element of any communication system. This paper gives a brief overview of the fundamentals, mechanism and importance of Forward Error Correction. The design and implementation of a (63,36,5) BCH Codec is also projected in the later sections. All simulations are made on MATLAB R2018b and the VHDL implementations have been carried out using Xilinx Vivado 2018.2.