Modelling pre-latching delay of track and latch comparator

摘要

The transient behavior of track and latch comparators is of great importance in designing a high speed comparator. This article models the pre-latching period of the evaluation phase of this type of comparators. An equation is presented which models the delay during this period with relatively good accuracy. The proposed equation can provide a better insight to the designer on the impact of different parameters on the delay.