Low-Complexity and Resource-Aware Compression Algorithm for FPGA Bitstreams

摘要

Since the logic density of modern FPGA devices has been increasing rapidly, FPGA bitstream compression has become a target for research. However, efficient compression algorithms usually involve high complexity, leading to high penalty in decompression resources. In this paper, a novel simple compression algorithm has been developed that can fairly reduce the bit-stream size without demanding any complexity in the decompression scheme. It has two modes of operation. The first mode is intra-bitstream which is implemented using runlength encoding that compresses consecutive repeated words. The other mode is inter-bitstream which is implemented using BitMask technique that eliminates redundant words among multiple bitstreams. On bitstreams with high utilization, our algorithm scores compression ratios of 59% ～ 77%, in compare to 42% ～ 80% for other hardware-implementable algorithms. Additionally, the required decompression resources are minimized. Moreover, the proposed algorithm addresses partial bitstreams of dynamically reconfigurable arrays. Our results show a 28% compression ratio for two relocated partial bitstreams. Finally, a Bitstream Compression Tool was developed to automate the process of compression optimization.