A high linearity input buffer is critical for a high speed high-resolution analog-to-digital converter (ADC), especially for IF/RF sampling applications. In this paper, a wide-band input buffer with optimized linearity for high-speed high-resolution ADC is proposed. The nonlinear sources of the input buffer are analyzed in detail and then six techniques including replica load, constant drain source voltage, mixed channel length, impedance boosting, programmable current source, and high frequency isolation are applied. Hence both low frequency and high frequency linearity of the input buffer are improved. The presented buffer is used to a 14 bit 500MSPS ADC, the measurement results show that, the buffer achieves 91.6dBFS SFDR and 68.7 dBFS SNDR at 10MHz input and maintains good performance until the input frequency increases to as high as 760MHz. The proposed technique improved the linearity of the wide band input buffer significantly.
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