SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification

摘要

Component reuse, complex buses and input/output connections add challenges to the SoC integration process. A large percentage of design integration errors comes from connectivity errors that may come from the connectivity specification or the SoC code generation scripts or both. Defining or documenting SoC connectivity is an error prone task by itself. SoC designers may use a standard for documenting SoC like IP-XACT, or have their own customized spreadsheets for describing the pin level connections, or they may not be using any method to specify SoC connectivity. This paper describes two approaches that enable SoC design and integration engineers with no connectivity specification to use Formal Verification to easily validate the connections on the SoC.