Reduction of delay variations in arithmetic circuits using a redundant representation

摘要

This paper investigates the impact of inter- and intra-die variations on binary and high-radix adders that adopt the borrow-save encoding. High-radix adders have been employed for the recoding of multipliers and for determining quotient and root digits in iterative division and square-root algorithms. These adders have been found to outperform conventional ripple-carry and carry-skip adders in certain applications, as they implement a carry-free addition algorithm. Carry-free addition using 4-to-2 compressors permits the accumulation of terms in constant time, independent of the word length of the operands. In order to estimate the delay distribution of the aforementioned adders, both Static and Dynamic Monte-Carlo Analysis are employed. Our analysis quantitatively proves that high-radix adders can achieve substantially more narrow delay distributions, i.e., they reduce the delay variance by 98.95% and 99.68% in comparison with 32-bit ripple-carry and carry-skip adders respectively as estimated by DMCA; therefore they are suitable for the implementation of variation-tolerant systems.