CMOS integrated circuits; adaptive equalisers; clock and data recovery circuits; decision feedback equalisers; radio receivers; CMOS; DFE adaption logic; DSL; ESL; adaptive quarter-rate 2-tap DFE; baud-rate CDR logic; bit rate 15 Gbit/s to 28 Gbit/s; data-sampler-lane; error-sampler-lane; hybrid alternate clock scheme; loss 32 dB; power 48 mW; size 65 nm; soft-decision technique; source-synchronous serial link receiver; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Clocks; Decision feedback equalizers; Latches; Receivers; Timing; CDR; CMOS; DFE; adaptive; baud-rate; receiver;
机译:36 GB / S自适应波特率CDR,用CTLE和1-TAP DFE在28-NM CMOS中
机译:在28nm CMOS中具有DFE和CTLE的22.5至32-Gb / s 3.2pJ / b无参考波特率数字CDR
机译:具有32 nm SOI CMOS技术的DFE接收器的1.4 pJ / bit,可扩展功率的16×12 Gb / s源同步I / O
机译:48MW 15至28GB / S源 - 同步接收器,采用混合交替时钟方案和波特率CDR在65nm CMOS中的自适应DFE
机译:具有自适应盲DFE的4Gbps CMOS背板接收器。
机译:0.6V倍压器和时钟比较器,用于65nm CmOs中基于相关的脉冲无线电UWB接收器