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QCA system design using blocks with vertically stacked active elements

机译:使用具有垂直堆叠有源元件的模块的QCA系统设计

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Quantum Dot Cellular Automata is one among the various technologies proposed by the International Technology Roadmap for Semiconductors (ITRS) as a viable alternative to CMOS. Circuits designed in QCA are potentially better with respect to speed, power and area when compared to their counter parts in CMOS. But as the circuit complexity increases, there is a linear growth in the horizontal area leading to lengthier interconnects with increased delay. To circumvent this problem we propose a new design paradigm using vertically stacked QCA cells. As the active elements are placed right one above the other in this new approach, the number of cells used for the interconnection will be drastically reduced. Thus would result in very compact designs. This technique provides greater flexibility in routing due to the availability of both vertical and horizontal planes. Each majority gate which forms the basic element of a QCA circuit/Block is implemented in a different layer; hence it explores a new concept of reusability in QCA along with the reduction of time for determination of errors. In this paper we establish this idea with the design of adders, subtractors, ripple adders, ripple adder cum subtractors using vertically stacked QCA circuits. These circuits are implemented using the least number of cells and minimum clocking zones. Results obtained by simulation show a maximum reduction in the number of cells used for the overall design by 77% and the cells used for the interconnection by 90% in comparison to their primitive counterparts respectively.
机译:量子点元胞自动机是国际半导体技术路线图(ITRS)提出的各种技术之一,可以替代CMOS。与CMOS中的计数器部件相比,采用QCA设计的电路在速度,功率和面积方面可能更好。但是,随着电路复杂度的增加,水平区域的线性增长导致互连线更长,延迟增加。为了解决这个问题,我们提出了一种使用垂直堆叠的QCA单元的新设计范例。在这种新方法中,由于有源元件彼此正对放置,用于互连的电池数量将大大减少。因此将导致非常紧凑的设计。由于垂直和水平平面的可用性,该技术在布线方面提供了更大的灵活性。构成QCA电路/模块基本元件的每个多数门都在不同的层中实现;因此,它探索了QCA中可重用性的新概念,并减少了确定错误的时间。在本文中,我们通过使用垂直堆叠QCA电路的加法器,减法器,纹波加法器,纹波加法器和减法器的设计来确立这一思想。这些电路使用最少数量的单元和最小时钟区域实现。通过仿真获得的结果表明,与原始设计相比,用于整体设计的单元数量最多减少了77%,用于互连的单元数量最多减少了90%。

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