CMOS digital integrated circuits; comparators (circuits); delta-sigma modulation; low-power electronics; power consumption; BW; CMOS technology; DR CT ΔΣ modulator; FOMW; Walden figure of merit; bandwidth 20 MHz; clock cycle; clock frequency; comparators; intrinsic excess loop delay compensation; power 5.1 mW; power consuming summation; power consumption; quantizer intrinsic ELD compensation; reference voltages; size 0.086 mm; size 130 nm; third-order continuous-time delta-sigma modulator; voltage 1.2 V; Bandwidth; Clocks; Gain; Modulation; Signal to noise ratio; Switches; Transistors;
机译:具有2.2 MHz带宽和90.4 dB SNDR的4.5 mW CT自耦合
机译:使用ELD补偿嵌入式SAB和DWA固有时域量化器的连续时间Delta-Sigma调制器
机译:一种100-MHz BW 72.6-DB-SNDRCTΔΣ调制器利用初步采样和量化
机译:具有量化器固有ELD补偿的5.1mW 74dB DR CTΔΣ调制器在20MHz BW中达到75fJ / conv.-step
机译:使用双驱动Mach-Zehnder调制器通过信号预失真在电域中进行色散补偿
机译:达到所需剂量的药物操作是儿科实践的固有方法但没有指导原则或证据支持
机译:双量化delta-sigma调制器中模拟积分器非理想性的影响和补偿