An Efficient Method for Using Transaction Level Assertions in a Class Based Verification Environment

摘要

Transaction level assertions are powerful way of abstracting property of a design. This paper talks about application of transaction level assertion in a transaction driven verification (TDV)environment and shows how assertions on meaningful collection of transactions from different verification component checks property of a design under verification (DUV) using SVA. In conventional class based transaction driven verification environment (example OVM, UVM), system verilog temporal assertions are possible only in design elements like module. So for modeling transaction level assertions, transactions are needed to pass from class environment to module/program block where the assertions are implemented. Here we are proposing a new method for doing transaction level assertions by exploiting concept of method ports and system verilog scoping rules.