A Chopper-Stabilized Lateral-BJT-Input Interface in 0.6??m CMOS for Capacitive Accelerometers

摘要

We present a prototype lateral-PNP (LPNP) BJT interface IC for an SOI capacitive accelerometer with a measured resolution of 6.3mug/VHz and an output noise floor of -118dBVradicHz for a gain of 204mV/g at extremely low frequencies. The resolution is improved by further reducing the low-frequency Vf noise and offset of the LPNP input interface using a chopper stabilization technique. The interface is designed and fabricated in a 3V 0.6mum CMOS process and interfaced with the accelerometer device with wire-bonds, where the accelerometer is fabricated on an SOI substrate using a simple process that yields high sensitivity in a small die size. The power consumption of the IC is 3.75mW with external clocking.