Low frequency dithering technique for linearization of voltage mode class-D amplifiers

摘要

This paper introduces a novel technique for simultaneous linearity and efficiency enhancement of class-D amplifiers by combining a low frequency sinusoid, known as dither, with a bandpass signal. The proposed technique improves the linearity due to dither averaging effect, and power efficiency, due to the reduction of reactive loss. The feasibility of the idea is verified through realization and measurement of a 65nm TSMC CMOS voltage mode class-D amplifier operating at 1 GHz. The drain efficiency is enhanced from 19.2 to 37 percent, while providing ACPR of −33dBc for the first adjacent WCDMA channel.